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| CY29943 2.5V or 3.3V 200-MHz 1:18 Clock Distribution Buffer Features * * * * * * * * * * 200-MHz clock support 2.5V or 3.3V operation LVPECL clock input LVCMOS-/LVTTL-compatible inputs 18 clock outputs: drive up to 36 clock lines 200 ps max. output-to-output skew Output Enable control Pin compatible with MPC942P Available in Industrial and Commercial 32-pin LQFP package Description The CY29943 is a low-voltage 200-MHz clock distribution buffer with an LVPECL-compatible input clock. All other control inputs are LVCMOS-/LVTTL-compatible. The eighteen outputs are 2.5V or 3.3V LVCMOS- or LVTTL-compatible and can drive 50 series or parallel terminated transmission lines. For series terminated transmission line, each output can drive one or two traces giving the device an effective fanout of 1:36. Low output-to-output skews make the CY29943 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. Block Diagram Pin Configuration Q0 Q1 Q2 VDD Q3 Q4 Q5 VSS VSS VSS OE NC PECL_CLK PECL_CLK# VDD VDD 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD PECL_CLK PECL_CLK# OE 18 Q0-Q17 CY29943 Q6 Q7 Q8 VDD Q9 Q10 Q11 VSS Cypress Semiconductor Corporation Document #: 38-07285 Rev. *C * 3901 North First Street * San Jose Q17 Q16 Q15 VSS Q14 Q13 Q12 VDD 9 10 11 12 13 14 15 16 * CA 95134 * 408-943-2600 Revised December 21, 2002 CY29943 Pin Description[1] Pin 5 6 3 9, 10, 11, 13, 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 7, 8, 16, 21, 29 1, 2, 12, 17, 25 4 Name PECL_CLK PECL_CLK# OE Q(17:0) VDD PWR I/O I, PU I, PD I, PU O PECL Input Clock PECL Input Clock Output Enable. When HIGH, all the outputs are enabled. When set LOW, the outputs are at high impedance. Clock Outputs Description VDD VSS NC 3.3V or 2.5V Power Supply Common Ground No Connection Note: 1. PD = internal pull-down, PU = internal pull-up. Document #: 38-07285 Rev. *C Page 2 of 7 CY29943 Maximum Ratings[2] Maximum Input Voltage Relative to VSS: ............. VSS - 0.3V Maximum Input Voltage Relative to VDD:............. VDD + 0.3V Storage Temperature: ................................ -65C to + 150C Operating Temperature: ................................ -40C to +85C Maximum ESD protection ............................................... 2 kV Maximum Power Supply: ................................................5.5V Maximum Input Current: ............................................20 mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD. Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters (VDD = 3.3V 5% or 2.5V 5%, VDDC = 3.3V 5% or 2.5V 5%, over the specified temperature range) Parameter VIL VIH IIL IIH VPP VCMR Description Input Low Voltage Input High Voltage Input Low Current[3] Input High Current[3] Peak-to-Peak Input Voltage Common Mode Range[4] PECL_CLK Output Low Voltage[5] Output High Voltage[5] Quiescent Supply Current Dynamic Supply Current VDD = 3.3V, Outputs @ 150 MHz, CL = 15 pF VDD = 3.3V, Outputs @ 200 MHz, CL = 15 pF VDD = 2.5V, Outputs @ 150 MHz, CL = 15 pF VDD = 2.5V, Outputs @ 200 MHz, CL = 15 pF Zout Cin Output Impedance Input Capacitance VDD = 3.3V VDD = 2.5V 8 10 VDD = 3.3V VDD = 2.5V IOL = 20 mA IOH = -20 mA, VDD = 3.3V IOH = -16 mA, VDD = 2.5V IDDQ IDD 2.4 2.0 5 285 335 200 240 12 15 4 16 20 pF 7 mA mA 500 VDD - 1.4 VDD - 1.0 Conditions Min. VSS 2.0 Typ. Max. 0.8 VDD -200 200 1000 VDD - 0.6 VDD - 0.6 0.5 V V Unit V V A A mV V VOL VOH Notes: 2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Inputs have pull-up/pull-down resistors that effect input current. 4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the "High" input is within the VCMR range and the input lies within the VPP specification. 5. Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines. Document #: 38-07285 Rev. *C Page 3 of 7 CY29943 AC Parameters[6] (VDD = 3.3V 5% or 2.5V 5%, VDDC = 3.3V 5% or 2.5V 5%, over the specified temperature range) Parameter Fmax Tpd FoutDC Tskew Tskew(pp) Tskew(pp) Tr/Tf Description Input Frequency PECL_CLK to Q Delay[7, 8] Output Duty Cycle[7, 8, 9] Output-to-Output Skew[7, 8] Part-to-Part Skew[10] Part-to-Part Skew[11] Output Clocks Rise/Fall Time[7, 8] 0.8V to 2.0V, VDD = 3.3V 0.5V to 1.8V, VDD = 2.5V 0.2 VDD = 3.3V VDD = 2.5V VDD = 3.3V VDD = 2.5V 2.0 2.6 40 3.5 4.0 Conditions Min. Typ. Max. 200 4.0 5.2 60 200 1.7 2.2 1.0 1.1 ns ns % ps ns Unit MHz ns Zo = 50 ohm Differential Pulse Generator Z = 50 ohm CY29943 DUT Zo = 50 ohm Zo = 50 ohm RT = 50 ohm RT = 50 ohm VTT VTT Figure 1. PECL_CLK CY29943 Test Reference for VCC = 3.3V and VCC = 2.5V PECL_CLK PECL_CLK VPP VCMR VCC Q VCC /2 tPD GND Figure 2. Propagation Delay (TPD) Test Reference Notes: 6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 7. Outputs driving 50 transmission lines. 8. Outputs loaded with 15 pF each. 9. See Figure 1. 10. Across temperature and voltage ranges, includes output skew. 11. For a specific temperature and voltage, includes output skew. Document #: 38-07285 Rev. *C Page 4 of 7 CY29943 VCC VCC /2 tP T0 GND DC = tP / T0 x 100% Figure 3. Output Duty Cycle (FoutDC) VCC VCC /2 GND VCC VCC /2 tSK(0) Figure 4. Output-to-Output Skew tsk(0) GND Document #: 38-07285 Rev. *C Page 5 of 7 CY29943 Ordering Information Part Number CY29943AI CY29943AIT CY29943AC CY29943ACT Package Type 32-pin LQFP 32-pin LQFP-Tape and Reel 32-pin LQFP 32-pin LQFP-Tape and Reel Production Flow Industrial, -40C to +85C Industrial, -40C to +85C Commercial, 0C to +70C Commercial, 0C to +70C Package Drawing and Dimensions 32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14 51-85088-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07285 Rev. *C Page 6 of 7 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY29943 Document History Page Document Title: CY29943 2.5V or 3.3V 200-MHz 1:18 Clock Distribution Buffer Document Number: 38-07285 REV. ** *A *B *C ECN NO. 111096 116779 118744 122877 Issue Date 02/07/02 08/14/02 09/18/02 12/21/02 Orig. of Change BRK HWT HWT RBI New data sheet Add Commercial Temperature range in the ordering Information Update output duty cycle on page 4 Add power up requirements to maximum rating information. Description of Change Document #: 38-07285 Rev. *C Page 7 of 7 |
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